It is common practice in the design of integrated circuits to connect different levels of metalization through via holes filled with tungsten plugs. As the dimensions in integrated circuits continue to shrink, the diameters of these via holes are similarly reduced. In general, the minimum separation between metal levels has not decreased at the same relative rate as have the diameters. As a consequence, the aspect ratio of a typical via hole can be quite high with values of the order of 10:1 not being unusual.
Proper filling of a via hole of narrow diameter (less about 0.3 microns) and high aspect ratio can present significant difficulties. In FIG. 1 we illustrate the kind of problem that can arise. Metal layer 3 (usually a line interconnection pattern shown in this case as running into the plane of the figure) is seen to be resting on silicon substrate 1. It has been covered by dielectric layer 2, its top surface planarized and a via hole etched through it down to the level of the metal. Barrier layer 13 was then deposited to act as a liner for the via hole which was then over-filled with tungsten layer 11.
Because of the small diameter of the via hole, when barrier layer 13 was laid down small cusps 12 built up at the mouth of the via hole. Then, while the tungsten was being deposited, the mouth of the via hole got bridged by metal before it could be entirely filled. The result of this was formation of void 15, commonly referred to as a key-hole. The presence of voids such as 15 cannot be allowed since the effective conductance of the tungsten plug is reduced and, more seriously, when tungsten layer 11 is later etched back (typically by means of chemical mechanical polishing or CMP) the key-hole gets exposed to the etch front and large amounts of plug material may be removed before the structure has been planarized.
In order to overcome this problem of key-hole formation, it has become common practice to widen the mouth of the via hole prior to the deposition of the tungsten. This not only removes protruding cusps such as 12 in FIG. 1 but serves also to widen the via hole at its mouth by beveling the edges. For example, Matthews et al. (U.S. Pat. No. 5,658,829) teach such a process. To accomplish this they make use of `facet` etching which is a process where the etchant that is used attacks both the photoresist as well as the dielectric layer, although significantly more slowly. Thus, while the depth of the etched hole is increasing, the diameter of the photoresist mask is also slowly increasing, resulting in a beveled edge to the via hole. Note that this method requires that the widening of the via hole take place before the barrier layer is deposited.
Other references of interest that were encountered during a routine search of the prior art include Ishii et al. (U.S. Pat. No. 5,313,100) who teach the use of anti-reflection coatings during the formation of the via holes. Additionally, their structure includes a rounded opening. Also of interest was Chen (U.S. Pat. No. 5,521,119) whose patent addresses the problem of contamination of the tungsten plug at the end of the CMP process. Contaminants formed in this way are removed through a post treatment involving argon ion sputtering.